The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device to be produced through the utilization of STI technique which is designed such that a gate insulation film and a gate electrode are successively formed at first and then a device isolating insulation film is buried, and also to a manufacturing method which is applicable to the manufacture of such a semiconductor device.
The STI (Shallow Trench Isolation) technique has been conventionally known as a device isolating technique which is adapted to be employed in the manufacture of a high-integrated memory such as an NAND type EEPROM, etc. This technique is featured in that a shallow trench is formed as a device isolating region on the surface of semiconductor substrate, and then, a device isolating insulation film is buried or filled in this groove. In the specific application of this STI technique, it is possible to utilize either [a] a system wherein a device isolating insulation film is buried in a groove at first, and then, a gate insulation film and a gate electrode are successively formed in a device region; or [b] a system wherein a gate insulation film and a gate electrode material film are successively formed all over the surface of substrate at first, and then, these gate electrode material film and gate insulation film as well as the surface of substrate are selectively etched away to form a groove, into which a device isolating insulation film is subsequently filled.
FIGS. 1A, 1B, and 2A to 2C schematically show one example of the conventional manufacturing process of the NAND type EEPROM, wherein the aforementioned system [b] is utilized. Specifically, FIG. 1A shows a plan view schematically illustrating one of the manufacturing steps; and FIG. 1B shows a cross-sectional view taken along the line 1Bxe2x80x941B of the structure shown in FIG. 1A. On the other hand, FIG. 2A shows a plan view schematically illustrating a post step subsequent to the step shown in FIGS. 1A and 1B; FIG. 2B shows a cross-sectional view taken along the line 2Bxe2x80x942B of the structure shown in FIG. 2A; and FIG. 2C shows a cross-sectional view taken along the line 2Cxe2x80x942C of the structure shown in FIG. 2A. By the way, in these FIGS. 1A, 1B, and 2A to 2C, the reference numeral 2 denotes a device region, and the reference numeral 4 denotes a device isolating insulation film defining the device isolating region.
According to the conventional manufacturing process of the NAND type EEPROM, wherein the aforementioned system [b] is utilized, a gate insulation film (tunnel insulation film) 5, a gate electrode material film 6a to be formed into a portion of a floating gate electrode, and a silicon nitride film 7 to be employed as a stopper film in a CMP (Chemical Mechanical Polishing) treatment are successively formed at first on the surface of a silicon substrate 1. Then, by making use of a resist pattern as a mask, the gate electrode material film 6a, the gate insulation film 5 and the surface of silicon substrate 1 are selectively etched away by means of RIE method, thereby forming a groove 3. Thereafter, the device isolating insulation film 4 is formed so as to fill the groove 3 with the device isolating insulation film 4, and the redundant portion of the device isolating insulation film 4 which is located outside the groove 3 is removed by means of CMP method, thereby obtaining the structure shown in FIGS. 1A and 1B.
Next, the silicon nitride film 7 is removed, and a regressing treatment to remove an upper portion of the device isolating insulation film 4 which protrudes from the groove 3 is performed. Then, a gate electrode material film 6b to be employed as a floating gate electrode 6 in combination with the gate electrode material film 6a is formed. After a slit is formed in each of the portions of the gate electrode material film 6b which are located respectively over the device isolating insulation film 4, an interlayer gate insulation film 8 is formed all over the gate electrode material film 6b including the slit portions. Then, a control gate electrode film 9 is formed on the surface of this interlayer gate insulation film 8. Subsequently, the control gate electrode film 9, the interlayer gate insulation film 8, the gate electrode material film 6b and the gate electrode material film 6a are patterned en bloc to obtain a structure as shown in FIGS. 2A to 2C.
In the structure shown in FIGS. 2A to 2C, the floating gate electrodes 6 adjacent to each other in the arraying direction of the control gate electrode 9 are required to be insulated from each other. However, according to the aforementioned method, since the upper portion of the device isolating insulation film 4 that protrudes from the groove 3 is reverse tapered in cross-section, a peripheral portion of the gate electrode material film 6a is caused to be located below the side surface of the device isolating insulation film 4. As a result, as shown in FIG. 2C, this peripheral portion of the gate electrode material film 6a which is located below the side surface of the device isolating insulation film 4 is failed to be etched and caused to be left remained thereat on the occasion of the patterning process of the gate electrode material film 6a. Namely, an etching residue 10 is caused to be produced between the control gate electrode 9 adjacent to each other. This etching residue 10 naturally invites the short circuit between adjacent floating gate electrodes 6 located in the arraying direction of the control gate electrode 9. Namely, the conventional manufacturing process of the NAND type EEPROM where the aforementioned system [b] is utilized is accompanied with the problem that the short circuit between floating gate electrodes is likely to be occurred.
The present invention has been achieved in view of the aforementioned problem, and therefore, an object of the present invention is to provide an STI technique wherein a gate insulation film and a gate electrode material film are successively formed at first and then, a device isolating film is buried, and which is improved so as to prevent the short circuit between the gate electrodes.
Another object of the present invention is to provide a semiconductor device and a manufacturing method of the semiconductor device, which are featured in that the occurrence of short circuit between gate electrodes can be substantially suppressed in the manufacturing process of semiconductor device.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, a transistor comprising a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film comprising a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising forming a laminate structure comprising a gate insulation film on a semiconductor substrate and a gate electrode material film on the gate insulation film, processing the gate electrode material film to obtain a gate electrode having a reverse tapered cross section, and forming a device isolating insulation film being in direct contact with a side surface of the gate electrode.
By the term xe2x80x9cforward taperedxe2x80x9d, it is meant that as far as it is employed with reference to a recessed portion such as groove, the width of the recessed portion decreases gradually from the opening portion thereof to the bottom portion thereof, whereas as far as it is employed with reference to a thin film, the width of the thin film decreases gradually from the bottom surface thereof to the top surface thereof. On the other hand, by the term xe2x80x9creverse taperedxe2x80x9d, it is meant that as far as it is employed with reference to a recessed portion such as groove, the width of the recessed portion increases gradually from the opening portion thereof to the bottom portion thereof, whereas as far as it is employed with reference to a thin film, the width of the thin film increases gradually from the bottom surface thereof to the top surface thereof.
As described above, according to the first and second aspects of the present invention, the gate electrode is formed so as to have a reverse tapered cross-section. If the gate electrode is formed into such a cross-sectional configuration, there would be little possibility that the patterning of the gate electrode is obstructed by the device isolating insulation film. Therefore, according to the first and second aspects of the present invention, it is possible to prevent the occurrence of short circuit between gate electrodes that might otherwise be induced by the etching residue.
By the way, the structure where at least part of side surface of the gate electrode is in direct contact with the side surface of the second portion of device isolating insulation film can be obtained only when the aforementioned system [b] is employed, so that it is impossible to obtain such a structure in the case where the aforementioned system [a] is employed. Namely, if it is tried to realize the same structure as mentioned above by making use of the aforementioned system [a], any kind of layer would be necessarily interposed between the gate electrode and the second portion of device isolating insulation film.
The method according to the second aspect of the present invention may further comprises, after the formation of the device isolating insulation film, removing a portion of the gate electrode to divide the gate electrode into a plurality of portions. Further, in the method according to the second aspect of the present invention, the device isolating insulation film may comprise a first portion which extends from a surface of the semiconductor substrate into an inner part of the semiconductor substrate and a second portion which protrudes from the surface of the semiconductor substrate.
In the method according to the second aspect, the processing of the gate electrode material film may comprise partially removing each of the semiconductor substrate, the gate insulation film and the gate electrode material film to obtain a groove, a bottom of the groove being constituted by the semiconductor substrate and sidewalls of the groove being constituted by the semiconductor substrate, the gate insulation film and the gate electrode. In this case, the formation of the device isolating insulation film may comprise forming a first device isolating insulation film on each of the sidewalls such that the first device isolating insulation film becomes thinner toward an opening of the groove, and forming a second device isolating insulation film in the groove after the formation of the first device isolating insulation film.
Alternatively, in the method according to the second aspect, the processing of the gate electrode material film may comprise partially removing the gate electrode material film to obtain a groove, a bottom of the groove being constituted by the semiconductor substrate and sidewalls of the groove being constituted by the gate electrode. In this case, the formation of the device isolating insulation film may comprise forming a first device isolating insulation film on each of the sidewalls, and forming a second device isolating insulation film in the groove after formation of the first device isolating insulation film.
In former case, the first device isolating insulation film may be formed by means of a deposition method. On the other hand, in latter case, the first device isolating insulation film may be formed by oxidizing a side surface of the gate electrode or by means of a deposition method.
The formation of the second device isolating insulation film may be performed such that a bottom of the second device isolating insulation film is lower in position than a interface between the gate insulation film and the semiconductor substrate.
In the method according to the second aspect of the present invention, the gate electrode may be formed by anisotropically etching the gate electrode material film.
In the method according to the second aspect of the present invention, the partial removal for obtaining the groove may be performed such that a width of the groove becomes wider toward an opening of the groove.
In the method according to the second aspect of the present invention, the device isolating insulation film to be employed for filling the groove should preferably be formed in two steps as mentioned above. Namely, a first device isolating insulation film is formed inside the groove in a manner to make the groove into a forward tapered configuration in cross-section, and then, a second device isolating insulation film is formed inside the groove so as to fill the groove with the second device isolating insulation film. According to this method, the occurrence of short circuit between the gate electrodes due to an inappropriate filling of the groove can be prevented.
In the first and second aspects of the present invention, the gate electrode may constitute at least a portion of floating gate electrode, and the transistor may further comprise an interlayer gate insulation film on the floating gate electrode and a control gate electrode on the interlayer insulation film. Namely, the transistor may be a non-volatile memory transistor.
In the first and second aspects of the present invention, the side surface of the first portion on the gate electrode side may be disposed contiguous with the side surface of the second portion on the gate electrode side. Alternatively, the side surface of the first portion on the gate electrode side may be disposed discontinuously with the side surface of the second portion on the gate electrode side, and still more, the width of the second portion is larger than the width of the first portion.
It is preferable in the first and second aspects of the present invention that the cross-section of the second portion is forward tapered. It is also preferable that the contacting face between the side surface of the gate electrode and the side surface of the second portion is inclined at an angle of not more than 100xc2x0 to the interface between the gate electrode and the gate insulation film.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.